Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI) for Semiconductor Wafer Manufacturing: A Genetically Optimised Framework for Reentrant Production Systems

Wafer fabrication exhibits unique characteristics, including reentrant process flows, variable bottlenecks, and highly variable process conditions. In order to identify the most severe bottleneck at each moment in time for semiconductor wafer fabrication, this research presents the Dynamic Multi-Criteria Bottleneck Severity Index (DMBSI), a new, data-driven methodology for analysing multiple diagnostic signals of cycle time to changes in process parameters, and the impact of reworks on cycle time in order to generate an interpretable, unified measure of bottleneck severity. The experimental validation of DMBSI was conducted using Manufacturing Execution System (MES) logs collected from 22 wafer production lots at a commercial 200 mm wafer fabrication line operated by Seagate Technology. Using 5-fold cross-validation, the GA-optimised DMBSI achieves a Pearson correlation of r = 0.80 with observed cycle-time contributions, representing an 8.1% improvement over the expert heuristic baseline (r = 0.74) and substantially outperforming the Theory of Constraints (TOC; r = 0.60) and Value Stream Mapping (VSM; r = -0.30). Furthermore, the unique time-windowed component of DMBSI enabled the identification of temporal bottleneck migration patterns, which shifted from the dominant constraints associated with dielectric deposition steps in the early production windows to those associated with over- and under-inspection in the later production windows. The integrated what-if counterfactual analysis demonstrated that a 50% reduction in waiting time at the top-ranked bottleneck step would reduce the mean cycle time by 7.2%, with the top five bottleneck steps offering a combined potential reduction of approximately 19%.