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Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
arXiv 2025
from 1 papers
Brucek Khailany
Chenhui Deng
Chia-Tung Ho
Haoxing Ren
Mingjie Liu
Nathaniel Pinckney
Wenfei Zhou