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Attribution
Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification
arXiv 2025
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
arXiv 2024
from 2 papers
Brucek Khailany
Haoxing Ren
Mingjie Liu
Chenhui Deng
Chia-Tung Ho
Christopher Batten
Wenfei Zhou
Yun-Da Tsai